Low-temperature Hybrid Bonding overturns 3D IC stacking limits: Lock and key Cu/SiO₂ structure triggers HBM4 generation

低溫 Hybrid Bonding 如何顛覆 3D IC 堆疊極限

1. Why is Hybrid Bonding the only way to continue Moore’s Law?

As traditional moiré scaling approaches its physical bottleneck and process costs soar, 3D heterogeneous integration is seen as the next golden generation. Hybrid Bonding combines copper-copper through-holes and oxide-oxide bonding into one, achieving **<10 µm** or even sub-micron vertical interconnection without relying on solder bumps; the signal path is shorter and the RC delay is lower, which is particularly attractive for high-bandwidth memory (HBM) required by AI/HPC.

Sony was the first to mass-produce CMOS image sensors in 2016, followed by imec, TSMC, Intel, Samsung, and others, which have since pushed the technology into HPC and memory chips.

低溫 Hybrid Bonding 顛覆 3D IC 堆疊極限

2. "Lock and Key": Design Thinking Founded by IBM

"Lock and Key" Hybrid Bonding, Learn in One Minute

element	Role	effect
Top copper pad/copper column	Lock	Provides a raised structure for electrical conduction and fixation
Bottom layer polymer holes (PI or SiO₂)	Key	Slightly larger and more flexible, it contains and locks the copper column

1. Insert first

   • After the two wafers are aligned, the copper pillars are pressed down into the polymer holes, like a key into a lock.

2. Lock it up again

   • During heat pressing at approximately 400 °C, the polymer temporarily softens and deforms, allowing the copper pillars to fit perfectly.

   • After cooling, the polymer rebounds and the copper column is tightly "stuck", combining mechanical strength and low resistance .

3. Benefits

   • It can compensate for surface irregularities and avoid gaps caused by hard collisions.

   • Without solder bumps, interconnect pitch can be pushed toward 10 µm or even sub-micron.

In a nutshell: Use a soft polymer "keyhole" to accommodate the copper "lock", and deform at high temperatures to achieve precise, reliable and low-resistance 3D vertical bonding.

3. Low temperature battle: Metal passivation layer allows bonding even at 40 °C

Why can the “metal passivation layer” reduce the Cu-Cu bonding temperature to 40 °C?

1. Oxygen-proof but not copper-proof

   • Copper will quickly form an oxide layer when it comes into contact with air. This layer of "rust" prevents copper atoms from diffusing with each other, so traditional Cu-Cu bonding needs to be heated to 300-400 °C to break through the oxide layer.

   • First , a very thin layer (≈10 nm) of inert gold, silver, palladium or titanium is plated on the copper surface, which is like putting an oxygen-proof coat on the copper - oxygen cannot enter, but the grain boundaries in the metal film are still "crack channels" for copper atoms.

2. Room temperature bonding, low temperature annealing

   • After the two wafers are aligned, they can be "glued" together at room temperature ~40 °C (primary bonding);

   • After that, only a short annealing at ≤150 °C is required, and the copper atoms penetrate along the grain boundaries to the opposite side, completing a dense metal continuum - completely avoiding the warping and stress caused by high temperatures.

3. Low temperature advantage in one go

   • Decompression/warping : The temperature difference is small and the wafer is not easily deformed.

   • Protect BEOL components : Downstream circuits, dielectric layers, and advanced transistors no longer have to worry about a 400 °C thermal budget.

   • Painless size reduction : The film is just an outer layer and does not change the grain structure of the copper itself, so it is applicable even if the pitch is further reduced.

In short, the metal passivation layer = copper's anti-rust film + atomic highway , freeing the Cu-Cu bonding from the constraints of high temperature, and being able to "stick firmly and quickly" even at 40 °C, becoming a key weapon for hybrid bonding to overcome high-layer HBM stacking.

IV. Inlaid Copper and DBI: From Dilemma to Inspiration

Damascene Cu and the core concepts of DBI — two points to understand in plain language

Scenario	Simple imagination	Key breakthrough
Dilemma: Depression on inlaid copper surface	After copper is filled into the "trench" of the silicon oxide layer, the surface will be slightly concave (about 20-50 nm). When the two wafers are to be bonded, the harder SiO₂ will touch first, but the concave copper will not touch → low yield.
Inspiration: DBI (Direct Bond Interconnect)	First, let the oxide layer "stick" to the oxide layer at room temperature (like sticking a tape), and then anneal at 400 ° C. Because the thermal expansion of copper is greater than that of SiO2, when heated, copper will "bulge" and automatically fill the depression , finally forming a copper-copper tight bond.	- No high pressure, no vacuum , short process time- Copper does not need to be fully aligned in advance, high tolerance for mass production

To sum it up in one sentence: first bond the oxide layer and then let the copper expand to fill the gap , and the original problem of "copper depression is difficult to bond" is turned into a high-throughput, high-yield DBI hybrid bonding technology.

5. Why does HBM4 require Hybrid Bonding?

generations	Overlay	Number of I/Os	Interface bandwidth	Mainstream Engagement	Yield pain points
HBM3E	12-Hi	2048	1.5 TB/s	TC-Bump	Breakthrough 12-Hi High Difficulty
HBM4	16-Hi	4096	2 TB/s	Hybrid Bonding	Bump Pitch is less than 20 µm, deformation and voids increase dramatically
HBM5	20-Hi	>4096	>2 TB/s	Hybrid Essential	TC-NCF cannot be shrunk any further

• Interconnection Pitch : From 40-25 µm to below 10 µm

• Signal integrity : lock and key pad are directly connected, reducing parasitics by 30-40%

• Thinning requirements : No bumps, reducing the stack thickness to 775 µm (still meets JEDEC standards after relaxation)

• Heat dissipation : Copper-copper continuity improves heat diffusion, which is beneficial for high-power AI GPU modules

6. Challenges and Prospects: Towards a Chiplet Ecosystem

• Alignment Accuracy vs. Panel-Level Productivity : How to Maintain >90% Bond Yield at 0.5 µm Pitch

• Thermal management : Fine-pitch bonding will cause local heat flux concentration, requiring the integration of micro-channel or CVD diamond heat sinks

• Design tool chain : EDA must consider electrical-thermal-mechanical coupling

Hybrid Bonding is no longer just a packaging step, but a degree of freedom in architecture design . The low-temperature "lock and key" Cu/SiO₂ solves the two major pain points of thermal budget and mechanical stress, making HBM4 and higher-layer memory stacking a reality, and paving the way for large-scale mass production of chiplet-based server CPU/GPU.

VII. Conclusion: Hybrid Bonding is a new key to breaking the limit

Low-temperature Hybrid Bonding opens the next door to 3D IC with a "key". When copper-copper interconnects are no longer constrained by temperature, sag, and oxidation, when the pitch drops to the nanometer level and the number of layers exceeds 20 Hi, future AI accelerators, ultra-large-scale memories, and heterogeneous SoCs will be available with unprecedented density and efficiency. For Taiwan's supply chain, whoever can master the low-temperature process, alignment control, and mass production equipment the fastest will hold the "master key" to accelerate the evolution of HBM4—and even the entire chiplet ecosystem.